Hi Experts,
We would like to ask assistance on this query:
I am after info on the ADS1174 ADC. If it's configured to SPI TDM output format, and CH1-4 reads are commenced on a DRDY hi>lo transition but NOT COMPLETED prior to the next DRDY hi>lo (due to a relatively slow fSCLK), will the ADC output data stream reset to start transmitting the new CH1-4 results once this second DRDY transition occurs?
So do the unsent SPI clocks from the still-running read cycle output data from a new conversion, starting with CH1?
Thank you.
Regards,
Archie A.
