DAC37J82:DAC_PLL、Serdes_PLLのLOCK信号について

Please send your complete issue in English. We cannot read this post.

I'm sorry. Please tell me about the built-in PLL. DAC_PLL, Serdes_PLL Both stop the clock once Change the clock frequency. Please tell me the LOCK time of DAC_PLL and Serdes_PLL at this time. Input clock jitter should be within specification. Also, what are the factors that slow down the LOCK signal? (1) Please tell me the LOCK time of DAC_PLL and Serdes_PLL at this time. (2) What is the factor that slows down the LOCK signal?

Yamauchi

This has not been measured. There are serval register writes required to get the PLL and serdes PLL to lock and another register read to get the lock status. The DAC PLL also requires to be tuned based on the reference clock and output frequency selected. This will take several spi writes. The SPI speed is the major delay related to the required lock time.

Regards,

Jim