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ADS4125: ADS41xx/58B18EVM applications

Mike Lin
Prodigy 30 points
Part Number: ADS4125
Other Parts Discussed in Thread: CDCE72010, ADS4129

Hi, 

I need to set up an environment to measure CVBS/COMET signals using ADS41xx/58B18EVM.

For EVM ADS4125's CLKP/M,

  • Select option 2
  • Install FLT1 and VCXO1

For EVM ADS4125's INP/M,

  • CVBS/COMET Tx chip

There are some questions, 

  • How can I sync them and be in phase if use the CVBS/COMET Tx chip instead of the red box below?
  • What is the LVDS data rate when running at the maximum ADC sample rate (125 MSPS)?
  • Can the LVDS data lanes be configured as 2-lanes or 4-lanes? Or is it just fixed 6-lanes?

Thanks a lot！

Best Regards,

Mike

  • +1
    TI__Guru* 91947 points

    Mike,

    I do not know anything about the CVBS/COMET Tx chip but if it has an input that can be used as a SYNC, you could install J20 and C122 on the ADC EVM and send a reference clock using the CDCE72010. This would be using output U7N.

    The LVDS rate is always double the sample rate so it will be at 250MHz with a 125MSPS sample rate clock.

    You can only use 6 lane mode. No other options are available.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 30 points

    The application we will use ADS4129 is as follows, please help to check if there's any problem.

    • VCXO provides 148.5MHz to CDCE72010
    • CDCE72010 CLKOUT divided outputs 148.5MHz, 74.25MHz and 37.125MHz for ADS4129 CLKP/M
    • The reference clock for CDCE72010 is calculated as 3.021MHz
    • ADS4129 INP/M inputs are CVBS-like audio and video analog signals from CCTV chip

    Is the relationship between the CLKP/M input frequency and ADC sampling frequency, parallel CLKOUT, and LVDS CLKOUT as shown in the figure below?

    Thanks a lot！

    Best Regards,

    Mike

  • +1 in reply to Mike Lin
    TI__Guru* 91947 points

    Mike,

    Everything looks correct except for the reference clock. If you plan on locking the 148.5MHz VCXO to the 3.021MHz reference clock, the CDCE72010 PLL logic only has whole integer dividers. If the divider is set to 50, the VCXO will output 151.05MHz. If a divider of 49 is used, the VCXO output will be 148.029MHz. This is assuming these frequencies fall in the range of the VCXO. If you need a clock of 148.5MHz, the reference clock needs to change. 

    Regards,

    Jim

  • +1 in reply to jim s
    Prodigy 30 points

    Jim,

    I will change the VCXO output to 297MHz, and the REF output to 27MHz.

    FB divider is set to 16, the N divider is set to 110, the M divider is set to 160, the P divider is set to 2, and the Fout will output 148.5MHz.

    Is it right ?

    Thanks a lot！

    Best Regards,

    Mike

  • +1 in reply to Mike Lin
    TI__Mastermind 22580 points

    Hi Mike,

    Your divider values shown in the image above are correct and will work.

    Regards, Chase