DAC37J84EVM: Transport layer for DAC37J84EVM

Trang Tien Nguyen

Part Number: DAC37J84EVM
Other Parts Discussed in Thread: DAC37J84

Hi,

I am a beginner in FPGA design.

I would like to generate sine and cosine waves using DAC37J84EVM and Xilinx FPGA part no: Kintex-7 KC705.

I created the sine and cosine wave samples by using the CORDIC algorithm for FPGA. I would like to convert these waves to analog by using DAC37J84EVM.

I understand that FPGA and DAC37J84 EVM can communicate through JESD204B. However, I do not know how to make a transport layer program for DAC37J84EVM in FPGA to map the wave samples at DAC37J84EVM.

Could you give me an example of a transport layer program for DAC37J84EVM?

Thank you very much.

over 1 year ago

0 Kang Hsia over 1 year ago

TI__Guru 66044 points

Hi Trang,

The transport layer is within the JESD204 protocol itself. It is not a separate program.

As an example, you can look into TI's JESD204C IP

https://www.ti.com/tool/TI-JESD204-IP

-Kang

0 Trang Tien Nguyen over 1 year ago in reply to Kang Hsia

Prodigy 20 points

Dear Mr. Kang,

Thank you for your response.

I do not have TI's JESD204 IP. Even though I request TI's JESD204 IP a few times, however, TI always denies my request.

I generated the JESD 204 B Vivado IP core, it requires me to have to do the data formatting for the specific converter that I choose to interface with (in this case DAC37J84EVM).

0 Kang Hsia over 1 year ago in reply to Trang Tien Nguyen

TI__Guru 66044 points

Hi Trang,

You can refer to the LMFS format table in the datasheet to configure the Vivado Xilinx JESD204 IP

Xilinx should be able to provide documents on using their Vivado tools for the configuration.

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DAC37J84EVM: Transport layer for DAC37J84EVM