• Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 1038 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

reading from ADS7881

Orin Laney
Prodigy 10 points
Other Parts Discussed in Thread: ADS7881

5226.ADS7881readproblem.pdf

We have an ADS7881 converter that cycles continuously.  We build up a voltage on a capacitor, which eventually trips a comparator, which causes CONST! to go low.  When BUSY goes high, this resets the capacitor voltage to zero which makes CONVST! go high again, and a new accumulation cycle begins.  This seems to work well in that we see CONVST! and BUSY cycling continuously.

The problem arises when we try to read data.  CS! is tied low, and we bit bang the port to assert RD! but we get all ones back.  This is the bus default because it has pull-ups.  The attached schematic fragment shows how the converter is wired.  Is it OK, or should I look elsewhere?

Thx,

Orin

  • TI__Mastermind 44620 points

    Hi Orin,

    I looked over your schematic and your description of operation and I don't see anything fundamentally wrong with how the part is connected or being used. Have you probed any of the analog or digital inputs with an oscilloscope during operation and would it be possible for you to post some of them to this forum?

    Some possible issues that I would look into are:

    • Which edge of RD! are you capturing the data? There is a delay (td6) between RD! going LOW and when data is valid so it is better to read the data after the delay or on the rising edge of RD!.
    • Is the CONVST! signal from the comparator a clean signal?
    • Is there a quiet sampling time period before CONVST! goes low?
    • Is there sufficient time for both the sampling and conversion phases?
    • Is RD! held low for the entire read operation or is it only pulsed? If RD! is HIGH then the parallel output bus is three-stated.
    • Is it possible that the AD8220 could be saturated at the rail?

    It would be good to check CONVST!, BUSY, RD!, IN+, and D11-D0. If you can capture an oscilloscope screenshot please try to show CONVST!, BUSY, and RD!

    Regards,
    Chris