ADS4249: IBIS model behavior

Marvin Gasis Arcangel

Part Number: ADS4249

Hi Team,

A customer is using the ADS4249 IBIS Model and if they check zero transmission line using FPGA as load, signal starting (rising for 700mV), if we connected using transmission path and connected to Load signal rising for 0 level. Please see image below for reference:

Transmission line:

Could you please explain this scenario and how the IBIS model is behaving?..

Thanks in advance.

Regards,

Marvin

over 1 year ago

0 Rob Reeder over 1 year ago

TI__Mastermind 24550 points

HI Marvin,

We are looking into this. Please give me a few days and we will get back to you after we check out the IBIS model.

Regards,

Rob

0 Marvin Gasis Arcangel over 1 year ago in reply to Rob Reeder

TI__Genius 9755 points

Hi Rob,

Thank you kindly. I am looking forward to your response.

Regards,

Marvin

0 Marvin Gasis Arcangel over 1 year ago in reply to Rob Reeder

TI__Genius 9755 points

Hi Rob,

Thank you. Please let me know once you're done checking the model.

Regards,

Marvin

0 Rob Reeder over 1 year ago in reply to Marvin Gasis Arcangel

TI__Mastermind 24550 points

Hi Marvin,

I had one of my collogues do a simulation on what was provided above and we have determined the following:

Assuming the IBIS model is accurate, the CMOS outputs are pushed to their limits and can hit the datasheet frequencies until “ideal” conditions but in real world the clock is going to be a attenuated sinewave instead of a square wave.

We are recommending a buffer be added in the design after the first 22ohm resistor and a close to the outputs of the ADC as possible.

Regards,

Rob

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ADS4249: IBIS model behavior