AFE5832LPEVM: AFE5832LP Date sheet

Hello Rouzbeh, 

We're currently working through a lot of demand right now. Allow me to get the experts for this device looped in. They'll reply by end of day, Friday. 

Kind regards,
Nick Z

Hi Rouzbeh,

Sorry for the confusion in the datasheet.

Let me explain the same:

The device is 32 Channel, but the number of ADC is 16. Hence 2 channels are time multiplexed with 1 ADC. Hence, with respect to individual channel, the sampling clock will be half of what you are providing to the ADC.

In other words, the data sheet describes a parameter Fc (adc conversion rate) which is the input clock to the ADC.

Then the sampling frequency will become Fc/2.

For example: Fc = 80 MHz, then sample rate will be 80/2 = 40 MHz

For the above case, LVDS parameters shall be:

Output frame clock frequency (FCLK) = 40 MHz (should be equal to sample rate) 

Say, your serialization factor NSER is 12, then,

Output Bit Clock Frequency (DCLK) = 40 (FCLK) x 12 = 480 MHz

Output Data Rate  = 2 x DCLK frequency = 2 x 480 Msps = 960 Msps (The output data rate is 2 times dclk frequency because the LVDS IP in the device is DDR (Dual Data Rate) which means it uses both the rising edge and the falling edge)

I hope it is clear now. Let me fill in the blank for you:

Say your sampling speed is Fs is 30 MHz, You will have to give ADC clock Fc = 60 MHz

The AFE5832LP board consists of 32channels, 16 ADCs with 10 bits resolution, and NSER is 12? The bit clock is aligned with the center of the data. Well, I have a frame clock frequency of 30 MHz?, a bit clock of 360 MHz? and a data rate of 720 MSPS?

You can refer to the table from the datasheet as well. Its available on Page number 22.

Thanks & regards,

Abhishek

Dear Rouzbeh,

Thank you.

Do let me know if you face any problem related to the device. Unfortunately, FPGA related things, we cannot fully support.

Thanks for your understanding.

Regards,

Abhishek