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ADC12SJ1600: Some questions about timestamp

Part Number: ADC12SJ1600


Hi team,

Customer want to use timestamp and got some questions, hope you could help!

1. For TMSTP± input, how it mark the specific sample? By using A high-level voltage or a low-level voltage or a rising edge or a falling edge? 

2. if using a high/low level voltage, how long need the voltage last to mark the sample point? 

3. For TMSTP± input, what's its maximum frequency of the input signal? 

Thanks~

Rayna 

  • Hi Rayna,

    The Timestamp input act as a 1-bit ADC sampled inn parallel with the ADC cores and both have matched latency through the device. For example if timestamp is setting sample with each ADC sample and output and it output is added to LSB of each sample of ADC. when timestamp input is low the LSB of ADC samples will be low but when timestamp signal goes high the LSB will also go high.

    Regards,

    Neeraj

  • hi Gill,

    when timestamp input is low, how long it needs to last to take effect? if the ADC CLK is 1.6GHz, and sampling rate is 1.6Gsps, at every clock edge, the ADC will sample the analog signal. For timestamp input, if every sample need to be timestamped, can its input frequency be 1.6GHz? If not, what's the maximum input frequency?

    Rayna 

  • Hi Feng,

    The timestamp input is connected to a 1-bit ADC with a sampling rate of the ADC CLK ( example 1.6GHz).

    Can you please give me little bit of insight about the why you want to have 1.6GHz signal applied to timestamp input. 

    The only reason I can think of a customer would like to put a 1.6GHz signal into timestamp would be to monitor a phase/frequency drift between the signal present to timestamp and ADC CLK. Is that the intended use case?

    Regards,

    Neeraj 

  • Closing the post. Conversation taken offline.

    Regards,

    Neeraj