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ADS1232: ADS1232

Balaganesh R
Prodigy 30 points
Part Number: ADS1232

hello sir;

 what is the exact delay between SCLK high to SCLK low to get all 24 bit ADC DATA without any bit loss

  • 0
    TI__Guru** 113765 points

    Hi Balaganesh R,

    Welcome to the E2E forum!  I'm not sure what information you are asking for, but have you looked at the information in the ADS1232 datasheet and sections 8.3.11 and 8.3.12?  In section 8.3.11 it is recommended that the rise time and fall time of the SCLK signal be less than 50ns.  There is also a timing diagram Figure 8-9 that shows the high time and low time of the SCLK must be a minimum of 100ns.  With a 50% duty-cycle (equal high and low times) the maximum SCLK frequency is 5MHz (1/200ns).

    All 24-bits of data must be read from the ADC after completion of a conversion but before completion of the next conversion or data corruption can occur while reading the result.

    I hope that answers your question.  If not, please give more detail specifically as to what you are needing to know.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 30 points

    Thanks Sir;

            Sir as u told i already try the delay for SCLK High to Low 2mSec also for Low to High. But I got the various ADC result for same analog voltage. I cant get the stable result. 

    long ADS1232_read( bool Calibrating)
    {
    long int value = 0;
    int i=0;
    unsigned int waitingTime = 0;

    delay_ms(801);//Require 801msec delay

    while((PORTA.IN & (PIN5_bm)));                   //Wait for Data ready


    // Read 24 bits but 24th bit is sign bit
    for(i=0 ; i < 24; i++)
    {
                  PORTA.OUTSET = PIN6_bm; //_SCLK, HIGH
                  delay_ms(2);
                  if((PORTA.IN & (PIN5_bm)))
                  {
                           value = (value << 1) + 1;
                   }
                   if(!(PORTA.IN & (PIN5_bm)))
                   {
                            value = (value << 1) + 0;
                    }
                    PORTA.OUTCLR = PIN6_bm; //_SCLK, LOW
                    delay_ms(2);
    }

    if(Calibrating)
    {
    for(i=1 ; i >= 0; i--)              // 2 extra bits for calibrating
    {
    PORTA.OUTSET = PIN6_bm; //_SCLK, HIGH
    delay_ms(2);
    PORTA.OUTCLR = PIN6_bm; //_SCLK, LOW
    delay_ms(2);
    }
    }

    /* Bit 23 is acutally the sign bit. Shift by 8 to get it to the
    * right position (31), divide by 256 to restore the correct value.
    */
    value = (value << 8) / 256;

    if(!Calibrating)
    {
    PORTA.OUTSET = PIN6_bm; //_SCLK, HIGH
    delay_ms(2);
    PORTA.OUTCLR = PIN6_bm; //_SCLK, LOW
    delay_ms(2);
    }
    return value;
    }

  • 0 in reply to Balaganesh R
    TI__Guru** 113765 points

    Hi Balaganesh R,

    It appears from the code that you are using a bit-bang type solution to retrieve the data.  There are a few things that I see in your code that can cause issues.

    • At the top of the function you show a required delay of 801ms.  This delay only happens if the calibration sequence is issued.  There is no need to add a delay to your code.  The delay will take place internal to the ADC which when the calibration is requested takes place after the data are read from the device.  When 26 or more SCLKs are set to the ADC, the calibration routine will start and also force DRDY/DOUT high and valid data will be available from the ADC when DRDY/DOUT transitions low.
    • You are polling DRDY/DOUT for a low state, but the LSB of the previous result could be either high or low.  If it was low already, then the polling condition will see DRDY/DOUT as low and the incorrect result will be seen because the next conversion has not completed.  So when using a polling method to determine end of the conversion you need to read the previous conversion result using 24 SCLKs and send one more SCLK to force DRDY/DOUT high.  So you should being sending 25 total SCLKs when reading conversion data and if you wish to calibrate send 26 SCLKs.
    • To allow for longer processing delays in the main processing code loop you probably should be using a faster SCLK.  4ms period (2ms high + 2ms low) is a very slow clock (250 Hz).  I would suggest trying a faster clock that is a 4us period (2us high + 2us low) and 250kHz.

    Best regards,

    Bob B