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ADC08D1020: Question for DS

Part Number: ADC08D1020

Customer found these two problems that are not consistent with the description in the DS when they use ADC08D1020, Hoe can get your confirmation. 

1. About CALRUN 

As shown in the figure 2 below, it is the peripheral circuit  of ADC08D1020. And 14Pin is open, 127pin is used as CS of SPI, pull down the CAL (30 pin).

After power on, the power supply (yellow) and CALRun (red) are displayed as follows. It can be seen that after the first pulse, the second pulse appeared.

Since the customer configures 127pin as CS, they think that there should be no calibration delay to occur the second pulse, and CAL is always low at the same time. So why does the second pulse appear?

2.  It is mentioned in DS that even the chip is powered on, but if the clock has not yet appeared, the calibration will not been triggered, and the chip will work at low power consumption until the clock occurs. So, will power on calibration take place when there is no clock? The clock is coming, will calibration take place again?

Since the calibration circuit will not work when there is no clock on power-on, what is the reason for the first pulse of CALRun?


  • Hi Harry,

    We are looking into this and we will get back to you with an answer. Thank you for waiting.

    Regards, Camilo

  • Hi Harry,

    The second pulse appears because there is an initial high level on the CalRun output as the device is powering up. This goes low as soon as the internal logic has stabilized after power up, effectively after internal logic has been reset. This is not an indication of a valid calibration event.

    Then after some delay as determined by the short CalDly setting and the received CLK frequency the actual calibration event occurs. Which would be the second high in CalRun. For example, with a 1 GHz clock rate the delay should be around 67ms. ( 2^26 x 1/1GHz ) The 2^26 value comes from page 16 in the datasheet below.

    For proper operation/performance the CLK+/CLK- inputs must be AC coupled from the differential clock source. With these AC-coupled inputs, even when no clock signal is applied the high gain clock receiver will generate some toggling of logic inside the chip at an indeterminate frequency. This will result in a much longer than normal CalDly period and CalRun period, but the signals will still toggle. And the calibration result will be poor.

    If this does not solve the costumer’s question, could they provide a similar plot that also includes a probe of the applied CLK input signal?  If the CalDly based calibration happens before the CLK is stable or the die temperature has settled close to the operating point, then the performance will not be optimal.

    We highly recommend they perform an on-command calibration 60 seconds (or more) after power is applied to the ADC and the clock is stable. This will calibrate the device at conditions more closely related to the actual operating point.