Other Parts Discussed in Thread: LMK04828,
Hello,
I would like to have our schematic reviewed.
Also here are current clock rates
- CLKP/M: 160 MHz (to support 160 Msps sampling rate)
- SYSREFP/N: 10 or 20 MHz (?)
- SYNCP/M: they may be coming from the data source, which in our case is an FPGA
- Do they need to align with the octets or frames?
The line rate calculation per converter since there are two JESD204B lanes
- 160 Msps
- 12 bits
- 8B/10B coding -> 15 bits
- round up to 16 bits
- Line rate: 2.56 Gbps
Thank you,
Andrew