TI-JESD204-IP: Question about multiple IP usage and 4 lane usage

Shuyi Liu

Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADS54J60, DAC39J84EVM

Hi, I'm using xilinx vc707, DAC39j84evm and ADS54j60 evm board for my design. I start from the reference design and find I need to call the module 2 times for seperate DAC and ADC since they are using different FMC. I would like to use DAC with linerate 9.8 and ADC with the linerate 4.9, but find there will be error message if I change the linerate for RX and TX different in gtx_8b10b_rxtx ip. Do you have any idea how can I call the module TI_204c_IP two times but with different linerate?

Another question is I'm trying to use ADC in 4211 mode which means number of RX lane need to be 4. But after I change NUMBER_OF_RX_LANES to 4 and other parameters, error happened:

and vivado cannot open this path.

Is there anything wrong I did? How could I change the lanes to 4?

Thanks advance for your help.

over 3 years ago

0 jim s over 3 years ago

TI__Guru* 91947 points

Shuyi,

We are looking into this.

Regards,

Jim

0 Ameet Bagwe over 3 years ago in reply to jim s

TI__Intellectual 2550 points

Hi Shuyi,

You can address this by using the IP_ID attribute of the JESD IP. Kindly check the description in section 5.1 of the user guide. You can assign different ID's to the two JESD IP's. This parameter is passed down to the transceiver wrapper, which is the mgt_8b10b_wrap module. Inside the gtx_8b10b_rxtx.sv file, you can use the ID value to select between two instantiations of the transceiver.

Regards,

Ameet

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TI-JESD204-IP: Question about multiple IP usage and 4 lane usage