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TSC2046: The Output Data is incorrect timing

Part Number: TSC2046

Dear Specialists,

My customer is evaluating TSC2046 and have questions.

I was grateful if you could advise.


Regarding TSC2046,
The sequence below is not followed. What could be the cause?

・At the start of DOUT, BUSY falls quickly and tBD is illegal (Figure 2 in attached document)
・At the time of the first read after turning on the power, the fall of BUSY is slow, and tBDV is illegal (Figure 3 in the attached document).
・From the second read, the fall of DOUT is slow and tDV is violated (Figure 4 in the attached document).
・At the end of acquisition, the rise of DOUT is slow, and tTR is violated (Figure 5 in attached document)

The data sent by DIN is as follows.
・MODE: 12-bit conversion
・SER/DFR: Differential reference
・Power-down mode: power-down between conversions (PD1:0 PD0:0)

Question about TSC2046.docx


I appreciate your great help in advance.

Best regards,