Dear Specialists,
My customer is evaluating TSC2046 and have questions.
I was grateful if you could advise.
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Regarding TSC2046,
The sequence below is not followed. What could be the cause?
・At the start of DOUT, BUSY falls quickly and tBD is illegal (Figure 2 in attached document)
・At the time of the first read after turning on the power, the fall of BUSY is slow, and tBDV is illegal (Figure 3 in the attached document).
・From the second read, the fall of DOUT is slow and tDV is violated (Figure 4 in the attached document).
・At the end of acquisition, the rise of DOUT is slow, and tTR is violated (Figure 5 in attached document)
The data sent by DIN is as follows.
・MODE: 12-bit conversion
・SER/DFR: Differential reference
・Power-down mode: power-down between conversions (PD1:0 PD0:0)
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I appreciate your great help in advance.
Best regards,
Shinichi
