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ADS1259: /DRDY not always asserting at sampling rate

Part Number: ADS1259

I'm trying to use the 3 TI ADS1259 24-Bit Analog-to-Digital Converters to simultaneous sample generated 60Hz sine waves. The ADS1259s are configured for Gate Mode 3600 SPS with 3 byte Read Continuous mode. The communication is 4MHz SPI and each ADS1259 has its own Chip Select and Data Ready connected to the microcontoller. The START pins are pulled low and a soft START command is used.
When I only read data from a single ADS1259 I get a Data Ready transition every 278 uSec as expected and the data read over SPI is correct. When I try to communicate with 3 ADS1259 at the same time, the Data Ready transition sometimes does not occur at the 278 uSec interval. The Data Ready transition does occur again after missing one or more intervals. It does look like the Data Ready signal reappears at some multiple of the 278 uSec sampling interval. It's usually 1-5 intervals but I've seen up to 60. I don't see any conflicts in the Chip Select for the 3 ADS1259s. I can't analyze the incoming signal with such gaps in the sampling.

If it's meaningful, I too always see a 0 as bit 7 of register 0 which the data sheet indicates should always be 1. It appears the original post (https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/953825/ads1259-stopped-conversions)  was solved with a communication modification but does not elaborate.

  • Hi d verdello,

    Are all of the ADCs behaving the same way? Or is it just 1 or 2 of them?

    It would help to see the SPI communication during multiple conversions to understand what is going on. If you have a Saleae logic analyzer you can just send me the .sal file. If not please post screenshots including CS, DRDY, SCLK, DIN, and DOUT. Please also make sure the timescale is clearly visible.

    -Bryan