• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 380 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC3663: clock inputs for sample Clock(CLK) , Dclkin

Ken Zhang
Intellectual 2775 points
Part Number: ADC3663

hi,

      There are some questions about clock signals for  sample clock , Dclkin and Fclk for ADC3663. pls kindly help check them.

    1. Be sample clock for (CLKP/CLKN) and Dclkin must generated from a same clock generator?  if no,  what is the requirement to met IC's clock synchronization?

    2. In register 0x19 bit 7, FCLK signal comes from ADC or from DDC block. if  ox19 bit7=0, Fclk is generated by sample clock, is it right? if ox19 bit7 =1, Fclk is generated from DDC block. is it generated from Dclkin? 

    3.which clock generates Fclk, sample clock or Dclkin , or any one of sample clock and Dclkin ?

    4 Can Dclkin be generated from Fclk via a external clock generator in which Fclk is as input reference clock?

  • 0
    TI__Genius 14981 points

    Hi Ken,

    1. CLK and DCLK do not have to come from the same source. If they are generated from different sources, ensure that the sources are reference locked to each other. 

    2. Bit 7 of register 0x19 sets the source of the FCLK signal. If this bit is a 0, the FCLK is generated by the ADC. If this bit is a 1, FCLK is generated from DDC block. These options are independent of the CLK or DCLK. Setting this bit (0 or 1) will depend on the mode that you plan to run in. Please reference datasheet on page 61 in the detailed description for this register to determine the correct setting.

    3. Similar to the question above, FCLK is either generated by the ADC itself or by the DDC depending on the setting for register 0x19. 

    4. DCLKIN cannot be generated from FCLK, because FCLK is not an input to the ADC. FCLK is either generated by the ADC itself or by the DDC (please refer to the functional block diagram, datasheet pg. 28). The ADC3663 requires an external DCLKIN input. 

    Regards, Amy

  • 0 in reply to Amy
    TI__Intellectual 2775 points

    1. can you share the mechanism of FCLK generated by ADC itself  and by DDC?

    2.About above #4, does mean that Fclk only can be generated when both sample clock and DCLKIN exist?

  • +1 in reply to Ken Zhang
    TI__Mastermind 21415 points

    Ken, regarding your questions:

    Ken Zhang said:
    1. can you share the mechanism of FCLK generated by ADC itself  and by DDC?

     No, we cannot share this information.

    Ken Zhang said:
    2.About above #4, does mean that Fclk only can be generated when both sample clock and DCLKIN exist?

    This device requires both the sample clock and the DCLK, and will not operate without both clocks. As Amy mentioned, these clocks should share a common reference such that they are coherent or reference locked, either by using a common crystal reference into a dual output synthesizer or by any other means. The FCLK is generated based on the sample clock transition and is meant to signal to the processor the location of the MSB in the output data stream. That is all the information we can provide here. 

    Regards, Chase