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ADS42LB49: ADS42LB49

Part Number: ADS42LB49

Can the ADS42LB49 be configured in QDR mode to allow the DAFrame and DAClock to be used in the clocking for the B Channel Data?

Thank you for the help,

David

  • David,

    There may be some skew among two channels output clock (in 100s of ps), so it is best capture a channels data on same channels output clock.

    Datasheet numbers for output timing belong to a condition where same channel’s output clock and data are used to characterize timing (see section 6.11 Timing Requirements: QDR LVDS Mode).

     The min setup and hold times are already in 160ns and 230ns range and these numbers may degrade if you use different channel’s clock to capture output data.

     Furthermore, the skew itself may vary from device to device, so it may not be wise to compensate skew by using extra delay in FPGA for one channel data bus.

    Regards,

    Jim

  • Jim,

    Thank you for the support!

    David