Hi!
We want to connect a ADC12QJ1600 to a Xilinx FPGA.
Our prefered FPGA has "only" 4 tranceiver lanes, so we want to use 4 tranceiver lanes (D0..D3) of the ADC12QJ1600.
The JMODE 8 supports what we want to do (12-Bit, 64B/66B, 4 Lanes). Because our FPGA tranceiver supports up to 10,3125 Gbps, we could go up to ~833 MSa/s ADC sample rate on 4 channels.
My question: Would it be possible to switch over to JMODE 14 (12-Bit, 64B/66B, 8 Lanes) at run time WHILE STILL only 4 lanes (D0..D3) are connected? Sure, we won't got the data from the ADC channels C+D anymore because they are send on D4...D7. But we will be able to use the full ADC sample rate (1,6 GSa/s) on ADC channels A+B in this optional "turbo mode". To protect the unused but activated output drivers on the lane 4-7 of the ADC12QJ1600 at JMODE 14, we would simple terminate them with 100 ohm.
Do you see a protocol/handshaking problem or something like that what would prevent this operation (sending 4 ADC data on 8 lanes while reading only 2 ADC data on 4 lanes)?
Best Regards,
Andre
