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ADC32J45EVM: JESD204 ADC does not achieve ILA

Lucas Efcavitch
Prodigy 20 points
Part Number: ADC32J45EVM
Other Parts Discussed in Thread: ADC32J45

I have a ADC32J45EVM development board connected to a KCU105 FPGA development board. I want to read sample data with the JESD204B interface, but I can not get the link to establish CGA/ILA. My LMFSK is 2,2,2,2,10. I want 160MSPS. I am using subclass 2. When I start the FPGA everything on the receiver side is initialized, locked, and error free, but it waits forever with no CGA/ILA. If I manually tell the ADC to send alignment characters (using the GUI) the FPGA receives the K characters but never goes into ILA. I suspect the SYNC~ interface is to blame. When I measure the voltage on the SYNC~ pins it is at the correct level and behaves as expected (falling edge when link resets).

  • 0
    TI__Mastermind 18145 points

    Hi Lucas,

    My understanding of your current issue is that the ADC32J45 will not enter CGS on its own when SYNC~ is asserted high by the FPGA. However, by using the GUI you can force the ADC32J45 into CGS and thus the FPGA will receive the K28.5 characters. If so, it makes sense that the ADC does not enter ILA because SYNC~ is already low, and when the FPGA de-asserts SYNC~, the signal does not transition from high to low. I believe you are able to pulse SYNC~ at this time and it will move into the ILA phase. Let me discuss with our team to see if they know why the device is not entering CGS when SYNC~ is asserted high by the FPGA. Kindly await a response.

    Regards, Chase

  • +1 in reply to Chase W
    TI__Mastermind 18145 points

    Hi Lucas,

    The SYNC~ for this device behaves differently than in most of our other JESD interface devices as the link enters CGS phase on a rising edge of SYNC~ signal. Once CGS is completed, the FPGA should de-assert SYNC~ and then ILA phase will begin. We suspect the SYNC~ needs to be inverted at the FPGA.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 20 points

    That worked! I'm still working on getting sample data, but the status bits indicate that it has achieved CGA/ILA and data! Thank you so much.