I have the SDOUT driving a TXBN0304 to interface the 1.8V ADC's SPI to a 2.5V SPI bus and the voltage droops when not in readback mode.
The ADC establishes solid high and low levels during the read and while writing the register to change back to write mode. When the write mode is entered, the SDOUT voltage droops significantly to about 0.99V despite the translator's 1kohm pullup (suggesting 810uA leakage?!) because of the high levels on the other side of this direction-sensing device. This is a potential Vih/Vil issue for the translator as I don't gate the translators with the SPI Chip Select (I have a mix of SPI and other signals being translated). As it is, the voltage is drooping significantly a partial bit period before the CSn is deasserted.
The DIGITAL OUTPUTS (CMOS INTERFACE: SDOUT) section of the electrical characteristics table only includes Voh and Vol, not leakage. I'm trying to determine if I have a design issue or an assembly defect.
