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ADS131M02: sending command influence ADC sampling

Koji Ikeda
Expert 5635 points
Part Number: ADS131M02

Hello Support team,

Customer ask if SPI command influence ADC sampling behavior, could you support? To receive data, if not NULL but RREG(1byte) or WREG(1byte) is used, are there any influence to sampling behavior or receiving data?

Thanks,

Koji Ikeda

  • 0
    TI__Mastermind 38475 points

    Hi Koji,

    The command response for the NULL command is the contents of the STATUS register in the beginning of next frame.

    When RREG command is sent to the ADC, the response in the next frame will be either a single register data or multiple registers data according to the specified nnn nnnn in the RREG command word to the ADC. Please see the timing in the figure 8-23 and 8-24 in the datasheet. Notice that the ADC conversion data are not output in the frame following an RREG command to read multiple registers. The following timing shows the frame format when reading a single register with RREG command. 

    Please let me know if you have any further question.

    Best regards,

    Dale

  • 0 in reply to Dale Li
    TI__Expert 5635 points

    Hella Dale-san,

    Thank you for your support. Does RREG command have no influence to ADC sampling behavior and the ADC output data? How about WREG? WREG looks like to change register setting and influence the ADC behavior. After WREG, when sampling with WREG setting start and output?

    Thanks,

    Koji Ikeda 

  • 0 in reply to Koji Ikeda
    TI__Mastermind 38475 points

    Hi Koji,

    The RREG command does not influence ADC conversion and it only influence which register or how many register data will be output in the next frame. The WREG command itself does not influence conversion, however the register written by WREG command may affect internal digital filter (sinc3 and sinc3 + sinc1 filters) settling, Please see the feedback below..

    Best regards,

    Dale

  • 0 in reply to Dale Li
    TI__Mastermind 38475 points

    Hi Koji,

    I'm also trying to get more information from design team, I will get back to you as soon as I can. Thanks.

    Best regards,

    Dale

  • 0 in reply to Dale Li
    TI__Expert 5635 points

    Dale-san,

    Thank you for your support. Please let me know your feedback.

    Thanks,

    Koji Ikeda

  • 0 in reply to Koji Ikeda
    TI__Mastermind 38475 points

    Hi Koji,

    I'm still waiting for the team's feedback, I will let you once I get a feedback. Thanks for your patience.

    Best regards,

    Dale

  • +1 in reply to Dale Li
    TI__Mastermind 38475 points

    Hi Koji,

    Please see the feedback below:

    • For WREG of the gain, cal offset and cal gain, they will be applied to the filtering right away without any synchronization to the ADC clock. So it is possible that the ADC data output may not be reliable for the 1st output ADC data after WREG. The filter timing should not be affected though. 
    • For the OSR setting, it is recommended put the device in standby mode first.

    Thank you for your patience.

    Best regards,

    Dale