ADC12DL3200: Package pin delays

Andreas,

Is this request for the LVDS output pins?

The LVDS outputs are matched on package within 1.5mm.

Do you need better matching than the datasheet stated 75ps (within a lane) and 125ps (between lanes)?

Regards,

Jim

Yes this is for the LDVS output pins.

If possible we would like to have the individual pindelay (for each pin) so we can compensate for both the ADC and the FPGA allowing us to run with not much delay compensation in the FPGA.

Thanks