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ADS5287: ACLK, LCLK and Ramp Test Waveform Help

Part Number: ADS5287

Hello Support,

We are trying to get the test ramp waveform received into our FPGA without any drop out data.  I have attached the differential clock input signals.  The input clock signals have capacitor coupling as shown on the schematic.  The clock rate is 16MHz in and we are down sampling in our FPGA to 4MHz sample rate.

The raw ramp data is dumped into an excel spreadsheet and plotted as shown in screenshot.  As you can see most of the data is good BUT we have places where we get glitches on the data.  I have also attached a screenshot of the LCLK and the ACLK and there appears to be some jitter there.

There are registers on the part that can adjust the PLL but the descriptions in the spec are NOT very detailed about how to use them.  Looking for suggestions for the next step to get rid of our glitches (hardware mod? Or writes to PLL registers??)  Please help.




  ADS5287_Ramp_Output_Data.pdf ADS5287_Ramp_Output_Slower_Decimation.pdf

  • Hi Mike,

    Could you please attach the raw data in a csv format for us? I myself am not too familiar with this device, however, my take from reading the datasheet is the PLL registers are only meant for selecting the PLL range, not anything to do with tuning the PLL necessarily. What is the sample clock source? Also, note that some team members are beginning to go on holiday break, so responses may be slow and more exaggerated than usual.

    Regards, Chase

  • Hi Chase,

    Thank you for the quick reply. Here are the two .csv files of the ramp data. We are currently sending this data ramp to four of the available 8 channels, so the first channel is in column 6 in the csv file, the second is in column 7, the third in column 8 and the final one in column 9. The rest of the data is additional data that our board uses.

    I'll attach another picture of it, but our sample clock is a currently a differential clock running at 16MHz that is being produced in our FPGA.

    We have contacted TI support in the past to help us out with this part on this same project in the past, it might be worth taking a look at too. Let me know if you need any more information. I look forward to hearing from you soon and thank you for the help.




  • Hi Michael,

    Jumping in here, can you please try your same experiments but at a higher sampling rate? Near 50 or 60MSPS?

    Please let us know.



  • Michael,

    The only adjustments you can make is to flip the LCLK by 180 degrees, make it edge aligned with the data instead of centered align (Address 42), change the LVDS data and LCLK termination (Address 12) or change the LVDS drive strength (Address 11). Try adjusting these to see if this helps. I ran the TI ADS5287EVM at 16MHz, and saw no issues with the ramp pattern.

    Try capturing the data not using the decimate by 4 to take this function out of the loop.

    What are the trace lengths between the ADC and FPGA? Are they all length matched?