• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 47 subscribers
  • Views 200 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS4125: OE drivers' setting time after exiting STANDBY

Tomasz Ciesla
Intellectual 690 points
Part Number: ADS4125

Hi, I'm using STANDBY feature of ADS4125 thru SDATA input to save some power between data acquisitions. I did observe that we can save a bit more energy by using OE and STRANBY together. 
So I did program in FPGA OE = !STANDBY. Unfortunately it seems that when those both are used together there's a long settling time until valid data is present on outputs. I can't find it in the datasheet, can you tell me the maximum value? the problem does not occur when STANDBY is always low and only OE is applied 

Example:

CLKOUT for OE = always high:

 CLKOUT for OE = !STANDBY:

 

  • 0
    TI__Mastermind 22620 points

    Hi Tomasz,

    We don't have this kind of data or any reasonable means to take this kind of data. I would suggest to self-characterize this over many cycles yourself and then add σ/2 to the max recorded time for data to become valid. This should be a sufficient buffer.

    Regards, Chase

  • 0 in reply to Chase W
    TI__Mastermind 30660 points

    HI Tomasz,

    Also keep in mind that this ADC is a pipeline architecture. Therefore, any interrupt in the sampling process will cause delay and the pipe needs to flush 10 clock cycles before the next valid sample can be acquired on the output. 

    Also, see the section 9.1 in the datasheet.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Intellectual 690 points

    yes, but we sample @125MHz and the waveforms are 10us/div, Also the funny shape: CLKOUT not within 0 and 1.8V visible as black spots on the waveform is strange. When you zoom the waveform it is still there, it's not a presentation error of the oscilloscope. It looks more like inrush current than pipeline effect...

    I'm waiting 30us after STANDBY as in the datasheet. The CLKOUT works fine with STANDBY without OE, and with OE without STANDBY. But it's corrupted when both are applied. CLK IN is always present

  • +1 in reply to Tomasz Ciesla
    TI__Mastermind 22620 points

    Hi Tomasz,

    I'm not sure that we can offer any support on this likely unintentional power savings mode you have discovered. The design and characterization engineers know about all device features and therefore know about the potential for power savings while defining the device and selecting which features of the device shutdown to save power when the STANDBY is entered. If there was a potential to save any additional power reliably then it would be included in the STANDBY state.

    The best bet (if you'd like to pursue this additional power savings) will be to self-characterize the recovery time and decide if you are comfortable with the results, otherwise all I can suggest is to only use STANDBY alone without OE.

    Regards, Chase