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TLA2518: About RC filter setting of TLA2518...

Part Number: TLA2518
Other Parts Discussed in Thread: BP-ADS7128, ADS7128, ADS7038

Dear Sirs,

I am looking for TLA2518 EVM reference schematics but only ADS7038Q1EVM-PDK is available.

In the user guide, the RC setting of EVM is 1K and 330p.

However, in another design of BP-ADS7128 BoosterPackTm Plug-In Module, the RC setting is 10K and 160p.

Since TLA2518, ADS7128 and ADS7038 are similar function solution, may I have your suggestion that what setting of RD filter is proper for TLA2518?


  • Hi Peter,

    The best answer I can give you at the moment is 'it depends'...  The TLA2518 uses a convert start signal to begin the conversion process and then it goes into acquisition mode as soon as the conversion completes.  The longer the device is in acquisition mode, the more settling time you have to get the input sampled properly.  If you can tell me what sort of sample rate you intend to use, I can get you some approximate values to use as a starting point.  In the meantime, there is a TINA-TI sampling model for the TLA2528 (same device, different interface - I2C vs. SPI) that you can use to see how well the inputs are settling with different R/C values.  You can also use the Analog Engineer's Calculator tool to enter R and C values and see what the resulting data rates you can achieve with the TLA2518.

  • Dear Tom,

    Just updating the information for your reference.

    The solution that we want to replace with TLA2518 in customer side is TLC2308.

    Its sampling rate is only 500Ksps which means the customer input signal sampling rate is 500Ksps Max.

    May I have your suggestion for the recommended RC setting?


  • Hi Peter,

    At 500kSPS, you will still need an amplifier.  Assuming you use the fastest SCLK of 60MHz, the acquisition time will depend on the operating conditions - are you just taking the 12-bit conversion result?  Are you doing averaging, or 12-bit data plus CHID?  Averaging takes 16 SCLK cycles to retrieve data which will reduce the acquisition time.  If you are doing averaging with CHID, you need 20 SCLK cycles in total.  Here is an example result from the Analog Engineer's Calculator tool: