Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 231 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE5816: AFE5816

Carlos Julian Martin
Prodigy 120 points
Part Number: AFE5816

Hi,

According to the AFE5816 datasheet, "the ramp, toggle and pseudo-random sequence (PRBS) test patterns can be reset or syncronized by providing a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit" However, no additional info is given about the corresponding bit to do that. The same happen with MASK_TX_TRIG, which seems to be a missing field in the memory map. Any info about that?

Regards,
C.J.

  • +1
    TI__Expert 6790 points

    Hi CJ,

    Thanks for pointing out the same. 

    These two register bits for TX_TRIG and MASK_TX_TRIG are actually available in JD version of the device and are not there in the normal version of the device.

    In the JD version of the device, the TX_TRIG signal can be generated by one of two methods: either by using the TX_TRIG pin or the MANUAL_TX_SYNC register. This MANUAL_TX_SYNC register is available in the demod register map.

    Similarly, the MASK_TX_TRIG register is available in the JESD register map, it controls the affects of TX_TRIG on internal clock-phase resets.

    I think while making the datasheet, they must have missed to remove these descriptions from the datasheet. 

    I will make a note of the same and will ensure that in the next revisions of the datasheet, this error is rectified.

    Thanks & regards,

    Abhishek