Hi,
We’d appreciate your help:
We’re setting up ADS42JB69 which has 2 cores, to work with our Xilinx MPSOC Ultrascale+ FPGA.
We’re using licensed Xilinx’s JESD204 IPs meaning - a PHY IP and an RX IP.
How should the IPs be configured to work correctly with the TI ADS42JB69 2 cores, 2 lanes per each core?
Should we use - see image below:
a. 1 phy IP and 2 rx IPs?
b. 2 phy IPs and 2 rx IPs?
Something else?
Most importantly, if we use option b and the data is all in the same transceiver quad,
Can we use the same clock pins source for both phys? (meaning ref_clk_a and ref_clk_b are the same clock)
Many thanks.
