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ADS42LB69: Regarding the review of ADC & DAC (DAC5652A) design

Mastik Kumar
Prodigy 130 points
Part Number: ADS42LB69

I am attaching the adc-dac schematic.

Please review and let me know if any changes are required.adc_dac.pdf

Please let me know the LVDS voltage level for clock inputs & Output.

Please let me know the value of Vcm for DAC and ADC.

  • 0
    TI__Guru* 91947 points

    Mastik,

    We are reviewing your schematic. The VCM and LVDS numbers should be in the data sheets.

    Regards,

    Jim 

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Mastik,

    On ADC page:

    1. Need to DNI either the pull up or pull down resistors on CTRL1 and CTRL2. These inputs need to be high or low. Leaving both resistors in will create a voltage divider.

    2. Need to remove pull up on RESET. Same reason as #1.

    3. Add more decoupling caps to VA1.8V input pins. Should use one for each pin.

    4. Remove extra decoupling caps for VA3.3V_ADC.

    5. Add a bulk decoupling cap (10uF) for each supply.

    6. Need to add 3 decoupling caps for DV1.8V.

    For DAC page:

    1. Suggest using series dampening resistors on input data lines (DAC1_D9_D0 and DAC2_D9_D0) and place these as close as possible to the source (FPGA).

    2. Remove R1133.

    3. Add 50 Ohm termination resistor to all CLK inputs and place as close as possible to the DAC. Another option is to use one clock source for WRT, CLKA, CLKB, WRTB and use only one  termination resistor. An example of this can be seen in the schematic section of the attached User's Guide.

    4. Provide isolation between AVDD and DVDD. See attached User's Guide schematic.

    For amplifier page:

    Submit a post to the High Speed Amplifier forum.

    Regards,

    Jim

    slau139b.pdf