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# DAC8820: Characterization Data for Current Consumption during Code Change

Part Number: DAC8820
Other Parts Discussed in Thread: TIPD194

[1]
Do we have any characterization showing the digital/reference current consumption transients during an output code change/update?

[2]
The datasheet has Figure 7.
It seems like this graph shows the input current (Idd) per digital pin, given the instantaneous input voltage at the pin vs VDD.
Am I understanding it correctly?

[3]
If we don't have data for [1] then could you use the graph in [2] (Figure 7), assuming it was showing input current per digital pin,
to calculate the total input current based on how many input bits were changing state?

Also, does this graph work both ways?
That is, a rising edge from 0V to Vdd on the input shows this trend line, but do we track this trend line on a falling edge as well?

Or am I totally off?

• Hi Darren,

1. we do not have transient data.  We would expect virtually no transient current on the reference input, as the reference input impedance is constant.  Any minor charge injection should be removed by the reference decoupling/noise filtering capacitor.  Digital supply current would depend on the slew-rate of the digital inputs, but should also be completely removed by the decoupling capacitors on the digital supply pins.

2. Yes, that could be considered the "stead-state" current of the digital input pins if you were to slowly transition from a low to high signal.

3. Yes, you could use that the total peak current, but really I would think of this as a charge problem, i.e. how much charge will you need to supply during the transition.  The curve in figure 7 would need to integrated over time based on the slew time of the digital input.  Assuming a reasonably fast digital transition edge.  That charge should be easily supplied by local decoupling capacitors.

I would assume that you would see similar steady-state current in both directions.

Thanks,

Paul

• Hi Paul,

We are trying to decide what bypass capacitance for VDD should be used with an I/V configuration.
Our discussion above hints at transient currents as input bits change state, and the requirement for VDD bypass capacitance.

The EVM (Link) shows two 10uF caps (C11/C12) on the DAC8820 VDD (5V) line.
It looks like there is a 10uF cap by the connector, J5, but then it looks like there is also a 10uF cap for bypassing / providing required charge during transients.
This differs from the TIPD194 refererence design (Link) where the VDD caps (C11/C12) are just 0.1uF / 100pF.

Is 10uF the go-to bypass capacitance for the device, or is the capacitance from TIPD194 enough?

Regards,
Darren

• Hi Darren,

2×10µF is probably overkill, but keep in mind that usually it is not the device itself that requires bypass capacitance, but really the quality (noise and transients) of the supply source on the PCB.  If you have a low-noise power source, like an LDO and direct PCB routing, probably just a ~10nF cap would be fine to help with some current transients.  If you cannot guarantee this power supply, then an array of caps are recommend.  I generally look for a large cap at the source of the supply (~10µF), then a series of caps near the DAC to help with different noise frequencies.  Something like 100nF+1nF, or 10nF and 0.1nF.

Thanks,

Paul