Hello,
In the datasheet, Fig. 71, in the 10x mode the rising edge of the ADCLK sometimes occurs when DDR LCLK is low, and sometimes when DDR LCLK is high. Which makes sense due to the 2.5x clock ratios.
The confusing part is in Fig. 73. The location of the rising edge can be controlled to happen when LCLK is low (PHASE_DDR[1:0] = 10) or high (PHASE_DDR[1:0] = 00).
If I set PHASE_DDR[1:0] = 00, how will the timing diagram of ADCLK and LCLK look like?
Thanks!
Hi Mohammad,
In the 10x mode, you are right that there is toggling of the LCLK state at every alternate ADCLK rising edge.
In Fig. 73. for 10x mode, what we mean is that there is a deterministic time delay (T_D) between when sync pulse is given to the ADC (which resets the internal clock dividers) and the first valid ADCLKP and LCLKP phase. After that, it will toggle every alternate ADCLK rising edge as shown in Fig. 71.
We have not characterized T_D for this case and you will have to do that in your system.
To be fair, PHASE_DDR[1:0] programmability has been kept to navigate any LVDS timing related issues. From that point of view, in the 10x mode, due to the toggling, only two phases are possible on LCLKP (one setting for PHASE_DDR[1:0] = 0 or 2, another setting for PHASE_DDR[1:0] = 1 or 3)
Thanks,
Karthik
