Other Parts Discussed in Thread: DAC38J82
Hi there,
This is a follow up to the previous thread. Just got back to this project after again and tried the 150MSps configuration and it did not work.
Our current FPGA -> DAC runs at 250MSps symbol rate, the FPGA JESD204 line rate is 10Gbps for 4 lanes. Serdes rate is 2.5Gbps. JESD format is 42111. Interp=8x. DACCLKP/N pin clock frequency is 250Mhz and the SYSREF pulse frequency is 7.8125Mhz.
I pulled out our working 250MSPs DAC registers settings to try to compare and have a few questions. (VCO =8.9Ghz, RATE = "00" (Full))
1) The datasheet Table 3. Relationship between Lane Rate and SerDes PLL Output Frequency column LINE RATE, is this the total throughput (10Gbps) or the Serdes rate (2.5Gbps)? I assume it should be the total throughput. So the Serdes PLL clock is 2.5Ghz.
2) Figure 28. Reference Clock of SerDes PLL. what is the Serdes PLL REFCLK? Based on our setting in SRDS_CLK_CFG , the Serdes PLL REFCLK should be 8.9Ghz/4 = 2.225Ghz. But based on Table 4 with MPY at the value of x14, the SerDes PLL Refernce clock should be 2.5Ghz/5 = 500Mhz.
Please see the attached spreadsheet of the DAC register settings.
Thank you so much!
