ADS131M04-Q1: Behavior DRDY is not as expected and register values read are incorrect

 Hi Prakash,

I will look into the details and get back to you soon. Thanks.

Best regards,

Dale

Hi Dale,

Thanks for the response. Sure, I will be waiting.

Regards

 Hi Prakash,

Thank you for your patience.

To read a register, actually no need to wait for /DRDY signal, please see the following timing I just captured for reading CFG register(0x06 address) which was already written 0x0700 to enable Global-chop mode with a default delay in the previous step. As you can see, the register data (0x0700) was successfully shifted out on DOUT line in the 2nd frame without checking and waiting for /DRDY signal.

Best regards,

Dale

Hi Dale,

Thanks for the response.

I do agree for not waiting till /DRDY going low. But, I need to repeat the reading of same registers continuously without reading converted data. The captured wave showed the same where I am trying to read registers MODE, CLOCK and GAIN1 repeatedly without reading ADC data (Since I am working on ILA, it is very difficult to capture the value of registers in one shot read. So only I am reading them continuously). When I am doing this /DRDY doesn't behave as I wish.

In your reading, are you not reading the response for command? I couldn't make out SCLK being sent for reading the same, since it shows only for register value read. And for read registers, don't I need to send 6 word frame?

Regards

Hi Prakash,

My image only showed the timing for reading a single register. However, there is no problem to read multiple registers by modifying the command.

To read only a simple or multiple registers, no need to send 6 word frame. If you sent more words/SCLKs, you will get nothing in the rest of words except the register data in the first word.

The response for the command (0xA300) I sent in the first frame is 0x0700 in the next frame, it was already shown there.

I did not understand what you said "I couldn't make out SCLK being sent for reading the same, since it shows only for register value read", could you please clarify? I'm trying to understand your challenge. Also, were you able to correctly read a single register data like the timing in my image?

Best regards,

Dale

Hi Dale,

It's my bad. When nnn nnnn is 0 in the read command it does send only register data not response.

Ok noted. But as observed it is sending some data when I send 6 word frame (you can see in the screenshot of trailing mail) when I am reading more than 1 word. I didn't try reading only register read. Let me try.

Agreed.

I was meaning that why weren't there serial clock pulses to read response (acknowledgement for command). I was confused. Since you were reading single register content so, there won't be any response to command except the content of register itself. Ignore the query.

New queries:

If I keep ADC clock and serial clock (SCLK) as it is and connect capacitors at the input pins of VDDs to avoid any ripples, will there be any reduction in the /DRDY rate? I observed it as reduced by half.

I am attaching a screenshot for channel-1 connected with load cell (COD) and other 3 channels kept open. When I tried varying the load all other channels are also varying which reveals that there is a cross talk between channels. Why is it so?

The content of registers are as mentioned in the trailing message.

Regards

Hi Prakash,

Okay, thank you for your explanation.

The capacitor on VDD pins are used for power supply decoupling, I did not see any reason to affect the /DRDY signal if you did not change main clock or other configurations. To address the issue, please provide the timing of digital signal including /DRDY captured with an oscilloscope.

The crosstalk specification for this ADC is -120dB which is much better than others. I suppose you are using your own circuit board, this is a system level issue and the interference could be caused by layout. A proper pcb layout design is also important. For test purpose, I would suggest you to apply a DC signal or short input externally or internally and do not leave the unused channels floating.

Regards,

Dale

Hi Dale,

I will try to capture the signals and share.

Meantime what will be result on data if I enable /CS and read 1 word and disable and gain I repeat?

Regards

Hi Prakash,

To be clear, are these steps you want to check?

1. Enable /CS
2. Read 1 word:  read 1 word channel conversion data or read a specific register?
3. Disable /CS
4. Repeat step 1 to 3

Please note that the data will be shown in next frame.

Regards,

Dale

Hi Dale,

Sorry. We were busy in domain transformation so, couldn't respond you.

Exactly the same I wanted to check.

Would you be clear about which data will be in the next frame?

And, if CRC is disabled can skip it in reading as an output CRC?

Regards

Prakash

Hi Prakash,

I apologized for the late response. I was on vacation in the past week. I noticed that you already posted a new query and got a response from our team. 

When you read a register, the register data will be shown in next frame.

Regards,

Dale

Hi Dale,

How was your vacation?

Sorry, since I didn't get any response from you so, I thought this thread is closed and also I started working on ADS131M08 so created a new thread.

Yes, I received response. Thanks.

Actually I wanted to skip reading the CRC since it is not much needed in my case. So, now I can skip reading it if disabled in the MODE register.

I forgot to tell you about the cross talk. There was memory read issue which was resulting into cross talk. Now it's resolved. But the DRATE is yet to resolve.

Thanks

Prakash

Ok Dale.

Thanks for your time.

Regards