The EVM12DJ3200EVM user manual does not specify all board's FMC's IO. Hence I need more information on that, in order to safely verify compatibility with our intended KU115 dev platform.
We intend to only use the following EVM FMC connections, with 1.8V FPGA banks, with ADC in JMODE0:
- DA0-3 and DB0-3
- The SYNC_SE signal, at 1.8V
- FPGA_JESD_CLK_A
- GND
The questions that arise are:
- Does this set of signals suffice or does the EVM need other inputs/outputs besides external 5V power and some input RF signal to work?
- SYNC_SE appears to be expected at 3.3V, so is it correct that R25 needs to be modified to allow a 1.8V SYNC_SE signal?
- We want to avoid receiving the OVRx signals from the ADC since they can go >1.8V. We would disable them in the GUI, yet the GUI appears to be bugged and they appear hardcode disabled (in the OVR_CFG register). So we need confirmation that the GUI readout of the OVR_CFG is indeed correct and they are always disabled without risk.
- We intend to short TDO and TDI via J27
