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DAC121S101QML-SP: Rise/Fall Times for Digital Interface

Matty13763
Intellectual 440 points
Part Number: DAC121S101QML-SP
Other Parts Discussed in Thread: DAC121S101

Hi,

I was wondering if you had information on rise and fall times of the DAC121S101 digital interface, particularly of SCLK.

I did not see any mention of this in the datasheet.

Thanks,

Jeff

  • 0
    TI__Guru 54903 points

    Hi Jeff,

    As these are inputs, we really do not have any maximum or minimum rise/fall time requirements.  The only issue to keep in mind is that most digital inputs have a threshold where both the nmos and pmos gates can be active, usually when the input is about midsupply.  That can cause higher current consumption.  On most digital pins, this is not an issue as the input is at a high slew rate while in that voltage region, so the increase in current is sourced by the local decoupling/bypass capacitor.  If your digital input is very slow, and the input is in the higher current region for a long time, then your supply will be required to source more current, maybe ~10mA.   I dont really have a limit here, as it is not a problem to be in the higher current state from the device perspective.  I recommend a rise/fall time of <10µs.

    Thanks,

    Paul