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AFE5816: Define samples length/time

Part Number: AFE5816


We are currently working on integrating the AFE5816 component into our hardware, after the successful experience with the EVM card.

In the EVM card we had the ability to define the measurement length.
What is the best practice for defining the measurement size in the AFE5816 component?
Also, it is not clear to us what happens after the trigger signal arrives.

Does the measurement actually continue until the change of the PDN_GBL/FAST?

Thanks a lot


  • Hi Mosh,

    After configuring the device in particular settings, the device continuously transmit the data on the LVDS lanes. 

    The EVM (typically TSW1400), I suppose you were using the same, just stores the data on to the FPGA memory from the instant the capture button is pressed. The length of the data measured depends on the available memory on the FPGA card. Hence, we have provided flexibility to define the capture depth. 

    The best measurement length is defined by the application and the capability of the FPGA to handle that particular amount of data.

    The trigger signal is used to align/synchronize the data timing across multiple devices (in a typical application). It helps in achieving deterministic latency. After the application of trigger signal, the first data arrives after a predetermined number of ADC clock cycles.

    You can refer to section LVDS Data Rate Modes and LVDS Synchronization Operation for more details on the same.

    Thanks & regards,