Hi,
I'm using the CS lines (changing data between different CS rising edges) to clock in data instead of the WR line.
The datasheet doesn't describe the case in which WRn is tied low and CS_A/Bn are cycled to load data.
The block diagram shows CS and WR as topologically equivalent with regard to clock chain timing.
Is this right?
Should I use different values for setup and hold (than those specified for WRn) when using CS for loading data?
Thank you for your help!
Hi Michael,
I think you are talking about the highlighted case in the logic truth table which is a valid way to write to the DAC.
In this case you would only need to follow t3 and t4 shown for the CSA and CSB lines in the timing diagram. I assume there is some additional logic in the device that differentiates CSA/B from WR, but at least one of those signals needs to be held constant and the other needs a rising edge in order to load the data according to the truth table.
If you were to use the WR signal then t5 is just telling you that WR needs to be held low for 30ns for the rising edge to be recognized and load the data. You don't need to change any of the timings for CSA/B if you are keeping WR pulled low.
Best,
Katlynne Jones
