Hello, Experts,
Here is the schematics to generate Analog signals through A and B chan.
Data could be sent on I2C correctly, Addr.0X4C, (0x98 was sent), control byte 0x10 and Data 0x5555, but no output either A and B.
Thanks.

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Hello, Experts,
Here is the schematics to generate Analog signals through A and B chan.
Data could be sent on I2C correctly, Addr.0X4C, (0x98 was sent), control byte 0x10 and Data 0x5555, but no output either A and B.
Thanks.

Hi Joanna,
Can you share an oscilloscope screenshot of your write sequence to channel A? The command bit is correct to update channel A and your schematic looks fine as well. What is your I2C voltage level and SCL speed?
Best,
Katlynne Jones
Hi Joanna,
It looks like the voltage levels are at almost 4V based on your screenshot. Is it possible to test with a lower logic level? Or try increasing VDD to at least 4V? It is possible that you are damaging the device by applying a voltage higher than VDD to the digital input pins:

Best,
Katlynne Jones
Dear Katlynne,
It shows that VDD is 3.3v on schematics. In fact, I2C pullup and VDD are same voltage supplier, 3.65V on the board.
I disconnected the outputs of DAC8574 from all other circuits, still no luck to get output.
Joanna
Hi Joanna,
Got it. Do you know if your controller is releasing the I2C bus for the DAC to send the ACK signal? I'm not seeing that when I count every 9th clock from your screenshot. Can you try changing the I2C address to an incorrect address and make sure that the DAC NAK's and your controller stops the write cycle? It's hard to tell if the DAC is actually sending the ACK in your screenshot. It actually looks like there are extra clocks in between the address byte, the command bytes, and the two data bytes. I'd investigate why those are there on your controller's end.
In a separate test, can you measure the reference and VDD voltage while you are sending the write command to make sure there are no dips in the supply?
Best,
Katlynne Jones
Dear Katlynne,
I will try and let you know the result and watch the supply to see f it is clean.
I also counted the 9th clock, I saw the a low level over there. Per datasheet, I thought it was "ACK from DAC". wasn't it?
Thanks,
Joanna
Hi Joanna,
Yes, the ACK from the DAC is a low signal, but your controller needs to release the SDA line high first. It's not clear to me if that's happening or not. If you tested with the wrong I2C address then we should clearly see that the controller releases the SDA high and the DAC NACK's. It's just a test to make sure your controller is behaving correctly.
Best,
Katlynne Jones
Dear Katlynne,
I tested by using a wrong Addr. There was no expected wave below.

The following captured is w/ the correct address, SDA and VDD.
It shows clean VDD and complete messages from I2C. Seems inputs are good.

Hi Joanna,
That is great to hear, and thanks for updating me.
Feel free to reach out if you run into any more trouble.
Best,
Katlynne Jones
Hi Joanna,
Each output update takes 36 clock cycles including the address byte, control byte, and the two data bytes. You can calculate the update rate using: update frequency = clock_Frequency/#clocks. With your 80k clock then this would be 2.22kHz or 2.22kSPS.
Best,
Katlynne Jones