We have a question on ADC7251 Timing characteristics, especially on “TD_CKD0” timing parameter in page 8.
It seems that you had already received a similar question, but let us confirm it.
ADC7x51 specifications document describes the serial interface timing in chapter 6.8.
According from the timing table & figure 1, SDO-A/B data should output from SCLK with the delay parameter of “TD_CKD0”.
This timing parameter looks to be defined from SCLK positive edge, but is it possible to be defined from SCLK negative edge?
The maximum of “TD_CKD0” is characterized as 15ns, but our timing observation shows TD_CKD0=21.1ns from SCLK positive edge in RT condition.
If it was defined from negative edge, it looks make sense.
To summarize our question simply, is TD_CKD0 defined from SCLK positive edge?
Or does ADC7251 output SDOA/B with negative SCLK edge?
