Hi Team,
I now have two questions:
Configuration conditions:
Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8.
DEVCLK+/-=2048MHz. FPGA is xc7vx485tffg1158-2 of xilinx.
Question 1: Although the manual says that BIT RATE=ADC CLOCK *2, that is, the Line Rate of JESD204B=2.048*2=4.096Gbps, I still don't understand how the Line Rate is calculated? That is, the detailed calculation process.
Question 2: After the ADC12J2700 is connected to the JESD204B core of the xilinx FPGA, what should the data format output by the FPGA be? Because I want to parse out the data format for the following down-conversion.
I'd appreciate it if you could illustrate my issue at your earliest convenience.
Thanks,
Katherine