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ADC12J2700: Line Rate and Output Data Format

Part Number: ADC12J2700

Hi Team,

I now have two questions:

Configuration conditions:

Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8.

DEVCLK+/-=2048MHz. FPGA is xc7vx485tffg1158-2 of xilinx.

Question 1: Although the manual says that BIT RATE=ADC CLOCK *2, that is, the Line Rate of JESD204B=2.048*2=4.096Gbps, I still don't understand how the Line Rate is calculated? That is, the detailed calculation process.

Question 2: After the ADC12J2700 is connected to the JESD204B core of the xilinx FPGA, what should the data format output by the FPGA be? Because I want to parse out the data format for the following down-conversion.

I'd appreciate it if you could illustrate my issue at your earliest convenience.

Thanks,

Katherine

  • Katherine,

    For #1, see attached.

    For #2, this should be 12 bit parallel data. Not sure exactly what you are asking here. If this doesn't help, consult with Xilinx regarding the data format. 

    Regards,

    Jim

    ADC12J2700 bypass line rate.pptx

  • Hi Jim,

    1. I still have doubts about the calculation of question 1. According to the calculation formula of Line Rate, Line Rate=Fs * M * N' * 10/(8*L)=2048*8*2*10/(8*8)=5.12Gbps. Does it mean that 8bit data is sampled on a rising edge one time, and 8bit data is sampled on a falling edge another time, so the total number of sampled data in one Fs sampling period is 2048*8*2bits? M is equivalent to the number of channels of the ADC, and Fs is the sampling rate. If there is only one channel number, that is, M=1, it is equivalent to the total number of data in one sampling period being 2048*1*2bit? Thanks.

    2. For question 2, it still remains to be solved. I know it is 12bit data. But what is the arrangement of the data format it outputs from the FPGA? I can parse it only if I know the output data format, otherwise I can't do frequency conversion.

    Regards,

    Katherine

  • Katherine,

    For #1, N' is total number of bits per sample and that would be 16. With M = 1, your equation is now 2048*1*16*10/(8*8) = 5.12Gbps.

    For #2, you need to consult with Xilinx. Their JESD204B IP core determines this. See attached for more info.

    Regards,

    Jim

    3125.Xilinx JESD204B IP.pdfug774_jesd204_core_ip.pdf

  • Hi Jim,

    I posted this question for a customer. And below is his latest reply.

    For question 1, you could check Table 11. Serial Link Parameters in the manual where N'=12, not 16. We are in bypass mode. And I think your algorithm might not be correct. According to this formula 'Line Rate=Fs * M * N' * 10/(8*L)', in the case of M=1, you already have the same rate as the M=8 case calculated by the first PDF you sent me. Thus, it is incorrect. We want to be in sync. What about Fs=2048MHz, M=8, L=8, N'? Also, can ADC12J2700 use this formula Line Rate=Fs * M * N' * 10/(8*L) to calculate Line Rate?

    Regards,

    Katherine

  • Katherine,

    New info I just received regarding this:

    For DDC Bypass mode, the outputs bit rate is always 2x the ADC clock rate. For 2.048 GSPS the bit rate will be 4.096 Gb/s.

     The octet rate per ADC is not 2 octets, it is actually 1.5 octets per sample.

     

    In addition there are 4 bits added at the end of every frame, so there is an additional bit stuffing factor of 64/60.

     

    So we have 2.048GSPS * 1.5 Octets/s * 64/60 Outbits/ADCbits * 10 bits/octet = 32.768 Gbits/sec

     

    Divided by 8 lanes gives: 32.768/8 = 4.096 Gbits/sec.

  • Hi Jim,

    Here's the reply from the customer.

    For question 1. Could you calculate it according to the formal formula? The calculation result of the document you sent is different from the result of your earlier reply. LMF = 8,8,8. I recommend calculating it according to the formula Line Rate=Fs * M * N' * 10/(8*L). Fs=2048MHz,M=8,N'=12,L=8. This calculation result cannot be obtained.

    For question 2.I notice that you are giving a document, and I also have this document. This document does not describe the data format of the ADC12J2700 output by JESD204B. So I can't parse it out.

    Regards,

    Katherine

  • For #1, where did you get this formula from? I did not see this in the JESD204B standard.

    For #2, see table 12 of the data sheet.