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Original question:

DAC81404: Indication of Stable Power Output Other Than Waiting for Settling Time

DAC81404: communication issue

he dajiang
Prodigy 196 points

Part Number: DAC81404

I want to test the digital interface (SPI)  btw MCU/STMF411 and 81404.

One way to make sure SPI works as expected is to read device ID from it.

According to data sheet, two communication cycles are needed to read register value, provided that SDO-EN bit is set in SPICONFIG register, which I did.

Here is my code to read device ID:

  a_SPI2_RxBuf[0] = 0;
  a_SPI2_RxBuf[1] = 0;
  a_SPI2_RxBuf[2] = 0;
  /* 1st cycle to send read command */
  // Device ID Reg Address: 0x01; highest bit 1 for reading.
  a_SPI2_TxBuf[0] = 0x80 + 0x01;

  Dac81404_CS_Low();

  ... // SPI DMA code to tx/rx 3 bytes
  
  Dac81404_CS_High();

  /* 2nd cycle to receive */
  Dac81404_CS_Low();

  ... // SPI DMA code to tx/rx 3 bytes

  Dac81404_CS_High();

My problem is the 3 received bytes are not as expected: supposed to be 0x81, 0x0A60 (0x0298 << 2).

What I got are: 0x40, 0x8538.

My SPI code is working well because I have managed to use it to change the voltage output for a long time.

Only recently did I want to use it receive.

  • 0
    TI__Mastermind 42253 points

    Hi He,

    Akhilesh will be able to review this.

    It would be helpful if you could share an oscilloscope screenshot of the two SPI commands with CS, SCLK, SDI and SDO included. Is there a delay between lines 12 and 15 where CS is toggled from high to low? 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    Prodigy 196 points

    There is no delay btw line 12 and 14.

    I have made PCB boards, on which MCU and 81404 is connected, but those pins are not populated.

    As I mentioned, I have been using the PCB boards for almost a year, and have no problem using firmware to adjust 81404 voltage output.

    This reading back work is low-priority.

    Can you confirm that my coding logic is correct?

    Yesterday I did a test: putting a delay about 1us btw line 12 and 14, the result is the same.

  • +1 in reply to he dajiang
    TI__Guru 55763 points

    Hi He,

    It looks like your data is shifted by 1 bit on the readback.  This is usually caused by the wrong clock polarity or phase setting in the SPI bus.  When this happens, you can still sometimes get write or read commands to work.  I recommend that you confirm you SPI mode for the PHA and POL settings.  You can also use a scope to quickly check that the format matches the DAC requirements.

    Thanks

    Paul

  • 0 in reply to Paul_Frost
    Prodigy 196 points

    Hi Paul,

    Thx for the info.

    Most likely SPI mode is the reason.

    Please allow me some time to verify.

  • 0 in reply to Paul_Frost
    Prodigy 196 points

    I just did a test: change SPICONFIG to 0x60, previously it was 0x40, making FSDO = 1, i.e. SDO updates on SCLK falling edges.

    I did not change my MCU SPI mode.

    What I received is 0xC08530, which is (0x810A60 >> 1) + 0x800000, very close now.

    The data sheet does not mention what PHA and POL should be, does it?

    It only mentions SDIN clocks data on SCLK falling edge, and SDO is configurable by FSDO bit.

  • +1 in reply to he dajiang
    TI__Guru 55763 points

    I recommend that you confirm with a scope or logic analyzer that your clock format is complatable with our timing requirement.  The MCU's documentation will likely show the 4 possible combinations.  If you do not have a scope, I recommend that you just try all for combinations to see if you get the correct response.  changing the FSDO state will only fix the issue if one of the two settings are correct.

  • +1 in reply to Paul_Frost
    Prodigy 196 points

    I did try to change SPI settings and with one of it; my received data is 0x810A70, which I assume is correct.

    So the 81404 chip I have has device ID of 0x029C instead of 0x0298.