Other Parts Discussed in Thread: ADC3683
Hello,
I am planning to use the ADC3643 chip (also maybe ADC3683 later) in the following configuration: 64MHz sample clock, decimate by 32, 20 bit 2 wire DDR output. As far as I can calculate, the required DCLKIN would be 20MHz in this case.
Can I eliminate the need for a PLL, the following way: after each FCLK transition, emit a ten cycle burst of a 32 or 64 MHz clock? (Instead of a continuous 20 MHz clock?)
Regards,
Markoo Cebokli
