• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 96 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1278-SP: Clock pulse width for SPI

Richard Katz
Prodigy 45 points
Part Number: ADS1278-SP

Hi,

tSPW, the SCLK positive or negative pulse width, is specified as 0.4 of tCLK, minimum.

The data sheet also says that the tCLK minimum is 37 ns, implying a maximum frequency of about 27 MHz.

And 0.4 x 37 ns = ~15 ns.

My question is, is the real requirement that the minimum SCLK pulse width be greater than 15 ns?  Or is the requirement independent of frequency, and the duty cycle must be between 40% and 60%?

Thank you,

rich

  • 0
    TI__Mastermind 36150 points

    Hello Rich,

    Welcome to the TI E2E community.

    The minimum pulse high or low time for SCLK is relative to tCLK and not an absolute value. If f-SCLK=27MHz, then the minimum pulse width will be 15nsec as you noted, but this number will increase as the f-SCLK frequency decreases.

    Also, keep in mind that the maximum f-SCLK frequency is equal to f-CLK frequency, and that for best noise performance, we recommend that f-SCLK/f-CLK ratios be limited to 1, 1/2, 1/4, 1/8 and so forth.

    Regards,
    Keith Nicholas
    Precision ADC Applications