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ADS1234: Offset voltage unaffected by cal ?

Part Number: ADS1234
Other Parts Discussed in Thread: ADS124S06, ADS1232

Background:

Using an ADS1234

Generally it works well i.e. low noise and accurate.

I have a 4 layer board with a ground plane with appropriate decoupling of supplies (I believe).

Power dissipation of the board is low so any temperature gradient across the board is very low.

The filter capacitor is C0G

The reference voltage is 2.5V, stable and low noise

The digital supply is 3.0V, stable and low noise

The analog supply is 5V, stable and low noise

Gain is set to 1, sampling speed is 10 /s

Channels 1, 3 & 4 have identical signal conditioning connected.

Channel 2, which would otherwise be spare has a capacitor across it and then series resistors (1K metal film) to allow me to connect a voltage reference in production for system calibration. It would then be biased to midrail (2.5V)

I have 5 boards built.

They all demonstrate various different offset voltages which appear fairly uniform between channels (1, 2, 3 & 4)

In general the distribution of offset voltages is more than I would expect for so small a sample size.

One of them has 17uV of offset voltage which is at the very limit of the datasheet (from 5ppm * 2.5V (ref) + 2*(1k * 3nA)

I could believe that there is a problem with my signal conditioning circuitry (though when I characterise it I cannot find such a problem) but

on channel 2 if I connect the two resistors together (furthest from the ADC) there is very little scope for a bug to be hiding.

Also, when I execute a 'calibration' the nDRDY line goes high for 800ms (indicating that I am doing that correctly) but the offset that I measure doesn't change.

In fact, it makes no difference whether I ever do a calibration or not.

Summary:

2 concerns:

1) Cal never makes any difference at all

2) One could say that 17uV is < 18.5uV so it is in spec. The data sheet shows a low typical value for offset voltage indicating that the distribution of offsets is something similar to Gaussian so it seems unlikely that such a small sample size would show this corner case.

Any thoughts?

  • Hi Oscar,

    The ADS1234 self-offset calibration places an internal short at the mux and calibrates out the offset from the mux/PGA/modulator stages.  The offset does not account for any of the external offset due to the input chopping bias currents.

    What are you seeing for noise?  Does it meet the datasheet noise tables for peak-to-peak noise?

    Best regards,

    Bob B

  • Thank you for your response.
    Referring to Table 7-1 of the datasheet.
    With gain = 1 and 5V reference one should see 420nV rms and 1.79uVpp
    I have a 2.5V reference but otherwise the situation is similar
    #1
    I measure based on 41 contiguous conversions immediately after power on
    Offset 19.7 uV
    Noise 405 nVrms
    Noise pp 1.64 uV
    Reminder, this is with 100nF directly across the inputs and with a pair of 1K resistors on each input.
    #2
    Then, after a calibration
    Offset 19.2 uV
    Noise pp 1.64 uV
    Noise rms 391 nV
    #3
    As a further experiment I shorted channel 2's input together thus eliminating differential input current noise
    Now I measure
    Offset 2.89 uV
    Noise pp 1.94 uV
    Noise rms 410 nV
    Which is clearly much better. Yay!
    #4
    If I perform a calibration and repeat
    Now I measure
    Offset 3.29 uV
    Noise pp 2.09 uV
    Noise rms 432 nV
    I expected the offset to be brought down significantly here and that didn't happen
    As a further experiment I tried shorting channel 2's input pins directly together and added a decoupling capacitor to ground. This should be an ideal situation and eliminate the effect of input chopping current
    #5
    Now I measure
    Offset 2.56 uV
    Noise pp 1.64 uV
    Noise rms 283 nV
    #6
    If I perform a cal and repeat
    Now I measure
    Offset 2.23 uV
    Noise pp 1.94 uV
    Noise rms 528 nV
    Still more offset that I would have expected.
    This explains the bulk of my problem.I can now work on reducing the impedance seen by the ADC inputs.
    That said, I am still surprised that the offset with zero differential impedance is so high.
    I think the data sheet doesn't quantify input current noise (or did I miss it?). Do you have any data to design around?
    I won't mark this closed just yet to see if there is any other helpful input.
  • Hi Oscar,

    I wouldn't call it current noise as it is actually a sampling current.  At gains of 1 and 2, the ADC is basically a switched cap input (similar to a SAR).  At gains of 64 and 128 the input is a high impedance true PGA where the current is limited to the input chopping stage of the amplifier only.  This device is primarily designed for bridge applications where the external offset is calibrated out by software.  Issuing the self-offset calibration removes the internal ADC offset within the level of noise.  That is why you see slight differences between calibrations.

    You should be able to issue the self-offset calibration, set the input to '0' and capture the code returned.  You would then subtract that code from every successive  conversion result which should remove the offset from the result (to within the level of noise).  This is how it would be done in bridge application such as with a load cell.

    Best regards,

    Bob B

  • Thank you.

    I follow the distinction of current noise versus sampling current.

    Question 1

    Maybe I don't understand the idea of calibration. If one can set the input to zero, measure the offset and then subtract it from future measurements what is gained by using the 'calibration' function?

    I don't have a bridge and can't set the input to zero which is beginning to look unfortunate and I ask this for the benefit of others.

    Question 2

    Is it possible to quantify the characteristics of the sampling current? Thus one can design to those characteristics to achieve a required level of performance.

    e.g. the sampling frequency, the magnitude of the charge, the balance of the charge, effect of temperature and common mode voltage or differential voltage.

    or perhaps 'present less than X Ohms resistance to each input to achieve some level of performance'

    O

  • Question 1

    Maybe I don't understand the idea of calibration. If one can set the input to zero, measure the offset and then subtract it from future measurements what is gained by using the 'calibration' function?

    The ADS1234 is capable of resolving to a few nV when using the PGA at a gain of 128.  Offset drift of the ADC itself can be problematic at these levels.  So periodic offset calibration help to remove the offset drift of the PGA.  At a gain of 1 it is difficult to say how beneficial the calibration really is.  If the temperature remains fairly stable for the ADC overtime, it is doubtful that the calibration will be very helpful at gains of 1 or 2.

    Question 2

    Is it possible to quantify the characteristics of the sampling current? Thus one can design to those characteristics to achieve a required level of performance.

    The input is switched cap at gains of 1 and 2, and would be very similar to what is shown in the datasheet for the reference input circuit shown in Figure 8-3.  From the last set of data collected for this device the input current is pretty spread out and can vary a lot from device to device.  I think you would need to consider +/- 20nA.  Also, the current will vary over temperature due to the ESD diode leakage.  The leakage increases significantly above 65 deg C.

    Another option would be to use a newer device that has much lower bias current and leakage.  One such device is the ADS124S06.  The noise performance is not quite as good as the ADS1232, but the input currents is vastly reduced.

    Best regards,

    Bob B

  • Ok, that is very helpful.

    Will now close this.

    Thank you.