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ADS8866: Supply voltage connection and current consumption

Part Number: ADS8866

Hi Team,

I have two questions about ADS8866. Could you help me with the answer.

1) Is it possible to connect AVDD and VREF to the same power supply IC (using LDO) output 3.0V?

2) Do you know the current consumption of the digital part when fps=1kHz?

Best Regards,
Tom

  • Hello Tom,

    Yes, at lower data rates, you can connect AVDD and VREF to the same power supply.  I suggest you include a 47uF capacitor directly next to the ADS8866 REF input pin and ground.

    The average current will scale with data rate.  You can expect about 3uA average current draw for AVDD+VREF when operating at 1ksps.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hello Keith,

    I understand that the possibility of the connection between REF-pin and AVDD-pin and extrapolation of the current.
    Is it possible without side-effect that REF-pin, AVDD-pin and DVDD-pin are connected?

    I understand the power consumption of  ADS8866 can be decreased to operation duty, i.e. 1/10, using power-down mode. Is it correct?

    Regards,
    Tom

  • Hello Tom,

    Yes, you can connect REF-pin, AVDD-pin, and DVDD-pin to same power supply.  As I suggested before, include a 47uF capacitor directly next to the REF-pin.

    Since you are going to use the same supply for REF, AVDD, and DVDD it is important to keep all digital lines idle during conversion and also during the last part of the acquisition cycle.  I suggest using 4-wire operation so you can transfer data during the first part of the acquisition period, and then keep all digital lines quiet (idle-state) during the last part of the acquisition period.  After this time, toggle CONVST pin and then let the conversion complete before pulling DIN low (chip select) and clocking conversion data out of the device.

    Yes, the ADS8866 automatically enters power down mode after the conversion is complete.  The current consumption will scale linearly with data rate, down to <1uA at 0sps.

    Regards,
    Keith

  • Hello Keith,

    Thank you for your support.

    I understand that the power supply and quite digital part during conversion
    and the power consumption scale linearly with data rate.
    However there is no decsription about SCLK min frequency.
    Could you tell me ?

    Also tell me the power consumption of digital part at 1ksps and 100ksps.
    Figure 57. Power Scaling With Throughput in the ADS8866 datasheet shows only analog part.

    Regards,
    Tom

  • Hello Tom,

    There is no minimum SCLK frequency; SCLK can be as low as 0Hz.

    The power consumption for the digital entirely depends on the external load, which is typically capacitive.

    You can estimate using the following equation:

    Iavg=DVDD*C-load*f-SCLK

    DVDD is the digital supply voltage

    C-load is the external load capacitance, which depends on the board layout and the input capacitance of the MISO pin on the host MCU.

    f-SCLK is the SCLK frequency

    Regards,
    Keith