ADC3643: ADC364x: Common Mode Range for CLK Input

Ben L1

Part Number: ADC3643

The Clock Input spec's a typical input common mode voltage of 0.9, but not a min or max. What range can the common mode voltage be for the CLK input? For example, can I DC couple the CLK signal from an LVDS signal that has >250mV differential signal, but a common mode voltage of 1.25V?

over 2 years ago

0 Amy over 2 years ago

TI__Genius 15321 points

Hi Ben,

Does your application require DC coupling? If you use differential input, you can AC couple the signal and not worry about the Vcm level.

Regards, Amy

0 Ben L1 over 2 years ago in reply to Amy

Prodigy 220 points

It is unclear at this point. There is a preference to DC couple, but if that can't be done for this part, we will see if we can AC couple.

0 Amy over 2 years ago in reply to Ben L1

TI__Genius 15321 points

Hi Ben,

Sounds good. I am checking with our design team to get a range for the CLK input Vcm and should be able back to you tomorrow with the response.

Regards, Amy

+1 Rob Reeder over 2 years ago in reply to Amy

TI__Mastermind 43020 points

Hi Ben,

After discussing this with design, there is not a good way to interface the ADC's device clock to an LVDS signaling. I would strongly advise using two DC blocking caps between the LVDS driver you plan to use and the ADC. I would also recommend using an external 100ohm diff termination at or near the ADC as well. The signal chain would like as follows:

LVDS driver - diff traces - 100ohm diff term - DC blocking caps - ADC clock pins.

Regards,

Rob

0 Ben L1 over 2 years ago in reply to Rob Reeder

Prodigy 220 points

Got it. Thank you.

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ADC3643: ADC364x: Common Mode Range for CLK Input