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[FAQ] ADS131B26-Q1: How do I initialize the device (start-up routine) and take measurements with the ADCs?

Part Number: ADS131B26-Q1


I found the example C code for ADS131B26-Q1 on

The code includes the driver functions to communicate with the device, which is very helpful to start developing firmware for ADS131B26-Q1.
However I need further help to implement a proper start-up routine for the device and to start conversions on the various integrated ADCs.

Joachim Wuerker

  • Hello,

    the following sequence explains the basic steps to initialize the ADS131B26-Q1 and to start conversions on the various ADCs.

    • Power-up the device by applying the necessary power supplies.

    • Wait for the DRDYn pin to transition from low-to-high, which indicates the device is ready for communication.
      (Alternatively:  Wait t_POR, as specified in the datasheet, after the power supplies have settled to their final values.)
    • Optional step: Take the RESETn pin low and then high to reset device. This step is not required, because the device goes through a power-on reset sequence during power-up.

    • By default, all available ADCs in the device are enabled. Disable all ADCs that are not required in the application.
      Send single register write commands to set the respective ADCxy_EN bits to 0b (x = 1, 2, or 3 | y = A or B).

    • Configure the gain (GAINxy[1:0]) and data rate (OSR13y[2:0]) for ADC1A, ADC1B, ADC3A, and ADC3B as required by the application.
      Send single register write commands to configure the GAINxy[1:0] and OSR13y[2:0] bits.
      ADC1A and ADC3A convert simultaneously. The OSR13A[2:0] bit settings therefore apply to both ADC1A and ADC3A.
      The same is true for ADC1B and ADC3B and the OSR13B[2:0] bit setting.

    • Configure the sequence steps for ADC2A and ADC2B as required by the application.
      Set the desired sequencer operation mode using the SEQ2y_MODE[1:0] bits.
      Enable the required sequence steps by setting SEQ2y_STEPx_EN = 1b.
      Configure the gain (SEQ2y_STEPx_GAIN[1:0]) and multiplexer settings (SEQ2y_STEPx_CH_N, SEQ2y_STEPx_CH_P[3:0]) for the respective enabled sequence steps.

    • Start conversions of all ADCs.
      Send a single register write command to set STARTy = 1b and SEQ2y_START = 1b.

    • Monitor the DRDYn pin for a falling edge which indicates new conversions are available for ADC1A, ADC1B, ADC3A, and ADC3B.
      Send a NULL command to retrieve the conversion data for ADC1A, ADC1B, ADC3A, and ADC3B within a single SPI frame.
      Data for disabled ADCs are 000000h.

    • To retrieve conversion data for ADC2A and ADC2B send a read multiple register command to read from the SEQ2y_STEPx_DATA registers.

    Joachim Wuerker