Good afternoon,
We're looking at using the ADS1675 for our design but could not find a specification in the datasheet that shows the relationship between clock jitter tolerance and SNR. Are there additional resources that show this correlation (graph or specifications)?
Thanks for the help!
Hello Mitchell,
Welcome to the TI e2e community.
This TI Precision Labs presentation discusses jitter with over-sampling ADCs.
The equation used to calculate jitter is shown below:
OSR is the over-sampling ratio and Dynamic Range (DR) can be used as an estimate for SNR. The below table highlights the different OSR options in the ADS1675.
Fin is the maximum input signal frequency that will be sampled, and t-jitter can be solved using the above equation.
Setting the DR target in the jitter equation to 20dB greater than the actual Dynamic Range of the ADC (111+20=131dB for 125kSPS example) will reduce jitter related noise to a negligible level verses the ADC noise. Assuming the maximum input Nyquist frequency of 1/2*Fdata=1/2*125k=62.5kHz.
t-jitter = (SQRT(256)*10^(-131/20))/(2*pi*62500)
t-jitter=11.5ps-rms
Clock jitter less than 11.5ps will have negligible effects on total noise for input frequencies up to 62500Hz. If the maximum input frequency in your system is less, for example, 10kHz, then the maximum allowed jitter will increase.
t-jitter = (SQRT(256)*10^(-131/20))/(2*pi*10000)
t-jitter=71.8ps-rms
Please let me know if you have additional questions.
Regards,
Keith Nicholas
Precision ADC Applications
