• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 414 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDC118: Saturation of one channel affects signal on other channel. But not all equally, and it seems, that some are not affected at all.

Birger Neumann
Prodigy 115 points
Part Number: DDC118


Hi There,

we just found out that saturating / FullScale Signals on one channel will affect the other input channels. Some show a slight increase of signal values, others even a drop. And, using a symmetrical CONV signal, it seems that A and B Samples of the same channel are not affected in the same way. I found in this thread (e2e.ti.com/.../3352393 that the reason for that are ESD protection diodes and some other parasitic coupling effects.

Our application might have the situation that one channel, which is not delivering used/usefull data at that time, might be saturated for a short time, while other channels are delivering neccessary data at that time. It would be neccessary that the other data are not affected by that.

We are using only five inputs of  the eight input of the DDC118. The inputs used in our application are channel (AIN) 1,2,3,4 and 8. Channels 5,6 and 7 are unused and connected to GND.

It now looks like if e.g. channel 1 is saturating, it affects 2,3 and 4 but not 8; if 2 is saturating, it affects 1,3 and 4 but not 8; if 3 is saturating, it affects 1,2 and 4 but not 8; if 4 is saturating, it affects 1,2 and 3 but not 8; if 8 is saturating, it affects none of the other channels.

Is there an explanation for this different behaviour of the inputs? I could think about a grouping of the input protection diodes or some other chip-structure related grouping.

Or maybe it is influenced by the GND connection of the unused channels?

If you could confirm some of the above, or give another explanation for that different behaviour, it could help us to find a best performing variation of the input channels.

My hope would be that I could connect the channel, the might sometimes saturate (at the moment it is on channel 1) to e.g. channel 1 and the others to 5,6,7 and 8, (2,3,4 connected to GND) to get no, or at least a minimized influence on the signals.

Thank you and best regards,

Birger

  • 0
    TI__Mastermind 19815 points

    Hi,

    we will try to get back to you around 4/20.

  • 0
    TI__Mastermind 19815 points

    Hi,

    Apology for the delay.

    From the thread you mentioned, the engineer replied/commented below -

    "

    There were two different integration times alternating, for A and B sides of the same channel, one longer than the other.

    You only cared about one of the two (the shorter one) but the input signal was present during the two of them.

    As you increased the input signal, the previous sample (on the longer integration time) would start at one point saturating the input amplifier and affect the next sample, the one you cared about.

    Removing the saturation from the previous sample solved the problem.

    "

    "

    As the integrated current in a given integrator starts to exceed the full-scale charge of the integrator, the amplifier saturates and the integrator is no more in close loop.

    Whatever current comes after that in the same integration period, it still flows in the capacitor but now, as the output of the amplifier is set (by the saturation), the input actually starts rising (no virtual ground anymore).

    If this current/charge is large enough, eventually the voltage will raise to the point the input ESD turns on, taking part of that current to ground and limiting the input voltage to a diode drop (~0.4-0.6V).

    Even if one does not care about this because one doesn't want that sample anyhow, the problem is that this same voltage is across some parasitic capacitance at the input (input trace, detector capacitance...). I.e., that parasitic capacitance holds some charge at the end of the integration period.

    When one switches from one integration to the other (from A to B or vice versa) there is no reset of the input, it is simply disconnected from one integrator and connected back to the other (I believe almost with a make before break). So, that charge fruit of the saturation on the previous period, stored on that capacitor, gets dumped now into the integration of interest and that distorts the final result.

    "

    Thanks