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DAC5675A and ADS6143 hdl code

Luiz Gouveia
Prodigy 30 points
Other Parts Discussed in Thread: ADS6143, DAC5675A, ADS62P49

Hi All,

 

Can I be a bit lazy and ask for VHDL or verilog code for DAC5675A and ADS6143 components? In special the LVDS interface with Xilinx (Spartan 6), if possible.

 

Many thanks and best regards

 

Luiz

  • 0
    TI__Mastermind 29220 points

    Hi,

    if you provide an email address then I can send the Verilog source code for the TSW1200 that connects to the ADS6143 EVM.  The FPGA on the TSW1200 is a Virtex4, but I believe the Xilinx cells we used for the ADC interface are available in the Spartan 6.  (The IDDR cell and the IDELAY cell to adjust for meeting setup and hold timing.)  The default IDELAY tap setting is set for the Virtex4 timing, and you would have to determine the best IDELAY setting for the Spartan 6, which likely will be a different tap setting.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 30 points

    Hi Richard

    Can you send the code to gol_luiz (at) fastmail (dot) fm ? 

    And for DAC5675A? Is it similar?

     

    Thanks a lot

    Luiz

     

  • 0 in reply to Luiz Gouveia
    Prodigy 20 points

    Hi Richard,

     

    I'm working on ADS62P49 but as I've understood all the other posts in the forum, the verilog code you are providing works in general for all ADC.

    So can you please send the code also to my email at michael (dot) handwerker (at) aed-engineering com ?

     

    Thanks a lot,

    Michael

  • 0 in reply to Luiz Gouveia
    TI__Mastermind 29220 points

    For the ADC code, sent to the address provided. 

    The DAC code is not similar, as it was developed for an Altera and uses much of the Altera resources such as the Nios processor.  Another person in the group will have to respond to that portion of the request.

    Regards,

    Richard P.

  • 0 in reply to Michael Handwerker
    TI__Mastermind 29220 points

    Hi,

    I sent the code to the address provided, replacing the (dot) and (at) as needed and inserting a dot in front of the com.

    But the email was rejected at the receiving end for security policies.

    Quote:

    Your message wasn't delivered because of security policies. Microsoft Exchange will not try to redeliver this message for you. Please provide the following diagnostic text to your system administrator.

    The following organization rejected your message: mailin2.rzone.de.

     

    Unquote

    Regards,

    Richard P.

     

  • 0 in reply to Richard Prentice
    Prodigy 30 points

    Hi Richard,

     

    I received your email with the code and the block diagram image. Thanks a lot for that. Could you also send the DAC code as well and I will try to translate to xilinx?

     

    Regards

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hi Richard,

     

    that's strange, as I was not aware of a filter rejecting attachments in our IT.

    However, can you please send it again to my private mail at handwerkermichael(at)gmail(dot)com ?

     

    Thanks and best regards,

    Michael

  • 0 in reply to Michael Handwerker
    TI__Expert 5820 points

    Hello

    The TSW3100 pattern generator EVM is used to drive data into TI's DACs. We do not share the complete source code of TSW3100 (an Altera based solution) because it contains a lot more elements than just the LVDS interface, such as DDR controller, NIOS processor, Ethernet controller etc and is very complicated to support.

    The LVDS portion of verilog is attached if it can be of any help.

    Regards,


    TSW3100 FIFO Files.zip