Hi,
I'm hoping to design a battery powered Real time EEG and ECG data acquisition circuit around ADS1198.The data rate is 256 samples/sec from each input channel.
I chose it because 1. Low power consumption 2. Simultaneous sampling of multiple channels
I'm hoping to use at least 6 input channels.
My main concern is how ADS1198 provide real time simultaneous sampling of multiple input channels. What are the clock rates that I have to use in main Clk and SCLK?
Regards,
Chamila
Hi Chamila,
Welcome to the E2E forum! Excited to hear about your interests in the ADS1198. As you progress with this design you may find our EVM or design notes for the ADS1198 helpful. You can find the product page for the ADS1198 EVM here and the design notes FAQ for the ADS1198 and ADS1298 family of devices here.
As for your questions, I see you're asking for system clock and SCLK settings. The table describing configuration register 1 on page 42 of the ADS1198 datasheet will be of interest for your system clock questions, inserted below:
It's important to note the addendum at the end of this datasheet snippet ("(1) fCLK = 2.048MHz"). With fCLK = 2.048MHz and bits 2:0 set to 101 (fMOD/512) we get 250SPS, which is very close to your desired 256SPS. If we work this in reverse we can find your fCLK frequency...
fMOD = 256 (Desired sample rate) * 512 (divider set by bits 2:0) = 131072 Hz or 0.131072 MHz.
fMOD = fCLK/16 (as per the note at the top of the snippet above)
fCLK = 0.131072 MHz * 16 = 2.097152 MHz
As you can see, the fCLK frequency is close to 2.048MHz, as expected. You can play around with these divider numbers until you can find a clock source that is able to create the frequency you're interested in.
As for your SCLK. The minimum SCLK speed depends on how many channels and which channels you are using for your system. You mention that you want to use at least 6 of the available 8 channels. If you're using channels 0-5 then you may have a slower SCLK since you'll only need to get the status word and 6 channel's data out. If you're using channels 2-7 then you will need a slightly faster SCLK since you'll have to clock out the status word and all 8 channel's data (though you will just throw out the first two channel's data). You'll be looking at between 120 and 152 bits worth of data, all of which needs to come out of the converter before the next conversion is performed. Additionally, you'll need to consider the decoding time the ADS1198 takes to decode the opcodes sent over SPI, so you'll need some extra time.
Since you've mentioned that you want to provide "real time" data, I would suggest that you run the SCLK as fast as possible so that you can get the new data out and to the user as quickly as possible. The fastest SCLK speed varies depending on what voltage you have on DVDD. Between 2.7V and 3.6V on DVDD you can go up to 20MHz on SCLK, between 1.65V and 2.0V you can go up to around 15MHz on SCLK. With SCLK at 20MHz you should have no problem getting all of the data out with a 2.097152MHz fCLK and it's going to help your "real time" data be closer to real time.
