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dac5686 evm problem

Ju Wang
Prodigy 40 points
Other Parts Discussed in Thread: DAC5686

Hi,

I hooked up the board according to the user guide (page 11).

I feed a 25 Mhz clock to CLK2. The clock is generated from the PLL of a Stratix FPGA board.

The output from J5 is connected to a 200 MHz scope with 50 ohm termination.

I am expecting to see a 6.25 MHz sine wave, but what I saw is far from a sine function. It looks more like

that:

The frequency seems correct and the phase is quite stable.

Any suggestion?

Thanks!

J.W

 

  • 0
    TI__Guru 65944 points

    Hi,

    This will happen when the ratio between output frequency and the sampling rate is high. The DAC cannot generate enough points for a smoother transition. To minimize the transition, either reduce the output frequency or increase the sampling rate. 

    -KH

  • 0 in reply to Kang Hsia
    Prodigy 40 points

    Hi Kang,

    How do I set the output frequency in the DAC5686 control software? is it the NCO field? what value should I set? I believe that I

    followed the steps in the user guide quite closely so I really don;t understant why it is not working.

    Please bear with me as I am quite new to the field.

    Could you recommend me some more robust step-by-step testing manuel, if you happen to have such thing.

    Thanks!

     

    -JW

  • 0 in reply to Ju Wang
    Prodigy 40 points

    I accidently turned the NCO on and a sine wave appears on my scope, but I could only get a good sine wave (NCO) to 30 MHz. so should the NCO be turned on or

    turned off?

    I figured the problem might have something to do with the DAC5686 SPI software.

    The software come with the CD does not work with my windows vista, always saying communication problem with the parallel

    port. I download DAC5686 v2p0, which works but does not produce the same result as in the user guide. any help is appreciated.

  • 0 in reply to Ju Wang
    TI__Guru 65944 points

    Hi Ju Wang,

    The NCO is used to place the I/Q signal to the frequency you would like it to be. The maximum signal bandwidth out of the DAC is Fdac/2 (DAC sampling rate/2), or +/-Fdac/2 in the complete I/Q domain.

    For instance, if you programmed your FPGA for 10MHz I/Q sinewave, with the NCO programmed to be 10MHz, you could get 20MHz of sinewave at the DAC output. Of course, you will need to consider the signal could fold back for every fs/2 Nyquist zone.

    In conclusion, you can turn on or turn off the NCO. It really depends on your application and how you want to program the DAC or FPGA. The NCO is there to provide flexibility.

    -KH

     

  • 0 in reply to Kang Hsia
    Prodigy 40 points

    Kang, thanks for your anser. I am still wrestling with the board...

    I have the board in factory setting, no input data, a 10 Mhz clk2 driven by FPGA PLL , and the software configured as

    The out put at J5 looks like a sine wave at 1.5 Mhz

     

    Then I changed the NCO and IF to 320 and 32 Mhz, got a better sine wave, but half the frequency of the last one.

    when I cranking the clk2 to 30 MHz, the signal is lost. Could you help me making some

    sense of this thing?

     what is the highest frequency for clk2 input?